? semiconductor components industries, llc, 2007 march, 2007 ? rev. 0 1 publication order number: 74HC373/d 74HC373 octal 3?state non?inverting transparent latch high ? performance silicon ? gate cmos the 74HC373 is identical in pinout to the ls373. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. these latches appear transparent to data (i.e., the outputs change asynchronously) when latch enable is high. when latch enable goes low, data meeting the setup and hold time becomes latched. the output enable input does not affect the state of the latches, but when output enable is high, all device outputs are forced to the high ? impedance state. thus, data may be latched even when the outputs are not enabled. the hc373a is identical in function to the hc573a which has the data inputs on the opposite side of the package from the outputs to facilitate pc board layout. the hc373a is the non ? inverting version of the hc533a. features ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1.0 a ? high noise immunity characteristic of cmos devices ? in compliance with the jedec standard no. 7.0 a requirements ? esd performance: hbm 2000 v; machine model 200 v ? chip complexity: 186 fets or 46.5 equivalent gates ? this is a pb ? free device http://onsemi.com marking diagram hc373 = specific device code a = assembly location l = wafer lot y = year w = work week = pb ? free package see detailed ordering and shipping information in the package dimensions sect ion on page 3 of this data sheet. ordering information 1 20 hc 373 alyw tssop ? 20 dt suffix case 948e 1 20 (note: microdot may be in either location)
74HC373 http://onsemi.com 2 data inputs d0 d1 d2 d3 d4 d5 d6 d7 18 17 14 13 8 7 4 3 1 output enable 19 q0 q1 q2 q3 q4 q5 q6 q7 16 15 12 9 6 5 2 pin 20 = v cc pin 10 = gnd noninverting outputs 11 latch enable function table inputs output output latch enable enable d q lhhh lhll l l x no change hxxz x = don?t care z = high impedance q2 d1 d0 q0 output enable gnd q3 d3 d2 q1 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 q6 d6 d7 q7 v cc latch enable q4 d4 d5 q5 logic diagram pin assignment design criteria value units internal gate count* 46.5 ea internal gate propagation delay 1.5 ns internal gate power dissipation 5.0 w speed power product 0.0075 pj *equivalent to a two ? input nand gate.
74HC373 http://onsemi.com 3 ??????????????????????? ??????????????????????? v cc dc supply voltage (referenced to gnd) ? 0.5 to + 7.0 v v in dc input voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ? 0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 35 ma i cc dc supply current, v cc and gnd pins 75 ma p d power dissipation in still air, tssop package? 450 mw t stg storage temperature ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds (tssop package) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. ?derating ? tssop package: ? 6.1 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d). recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ? 55 + 125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns ordering information device package shipping ? 74HC373dtr2g tssop ? 20* 2500 units / reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *this package is inherently pb ? free. this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high ? impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
74HC373 http://onsemi.com 4 dc electrical characteristics (voltages referenced to gnd) guaranteed limit symbol parameter test conditions v cc (v) ? 55 to 25 c 85 c 125 c unit v ih minimum high ? level input voltage v out = v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low ? level input voltage v out = 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v v oh minimum high ? level output voltage v in = v ih |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.2 3.7 5.2 v ol maximum low ? level output voltage v in = v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v il |i out | 2.4 ma |i out | 6.0 ma |i out | 7.8 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.4 0.4 0.4 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i oz maximum three ? state leakage current output in high ? impedance state v in = v il or v ih v out = v cc or gnd 6.0 0.5 5.0 10 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4.0 40 40 a note: information on typical parametric values can be found in chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d).
74HC373 http://onsemi.com 5 ac electrical characteristics (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter v cc (v) guaranteed limit unit ? 55 to 25 c 85 c 125 c t plh t phl maximum propagation delay, input d to q (figures 1 and 5) 2.0 3.0 4.5 6.0 125 80 25 21 155 110 31 26 190 130 38 32 ns t plh t phl maximum propagation delay, latch enable to q (figures 2 and 5) 2.0 3.0 4.5 6.0 140 90 28 24 175 120 35 30 210 140 42 36 ns t plz t phz maximum propagation delay, output enable to q (figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns t pzl t pzh maximum propagation delay, output enable to q (figures 3 and 6) 2.0 3.0 4.5 6.0 150 100 30 26 190 125 38 33 225 150 45 38 ns t tlh t thl maximum output transition time, any output (figures 1 and 5) 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns c in maximum input capacitance 10 10 10 pf c out maximum three ? state output capacitance (output in high ? impedance state) 15 15 15 pf note: for propagation delays with loads other than 50 pf, and information on typical parametric values, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d). c pd power dissipation capacitance (per enabled output)* typical @ 25 c, v cc = 5.0 v pf 36 * used to determine the no ? load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the on semiconductor high ? speed cmos data book (dl129/d).
74HC373 http://onsemi.com 6 ????????????????????????????????? ????????????????????????????????? (c l = 50 pf, input t r = t f = 6.0 ns) symbol parameter figure v cc (v) guaranteed limit unit ? 55 to 25 c 85 c 125 c min max min max min max t su minimum setup time, input d to latch enable 4 2.0 3.0 4.5 6.0 25 20 5.0 5.0 30 25 6.0 6.0 40 30 8.0 7.0 ns t h minimum hold time, latch enable to input d 4 2.0 3.0 4.5 6.0 5.0 5.0 5.0 5.0 5.0 5.0 5 0 5.0 5.0 5.0 5.0 5.0 ns t w minimum pulse width, latch enable 2 2.0 3.0 4.5 6.0 60 23 12 10 75 27 15 13 90 32 18 15 ns t r , t f maximum input rise and fall times 1 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns switching waveforms v cc gnd t f t r input d q 10% 50% 90% 10% 50% 90% t tlh t plh t phl t thl v cc gnd 50% latch enable t plh t phl q t w 50% figure 1. figure 2. figure 3. figure 4. 50% 50% 1.3 v q t pzl t plz t pzh t phz 10% 90% v cc gnd high impedance v ol v oh high impedance q output enable 50% input d latch enable v cc v cc gnd gnd valid t h t su 50%
74HC373 http://onsemi.com 7 test circuits *includes all probe and jig capacitance c l * test point device under test output figure 5. figure 6. *includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k d0 3 dq le 2 q0 11 1 d1 4 dq le 5 q1 d2 7 dq le 6 q2 d3 8 dq le 9 q3 d4 13 dq le 12 q4 d5 14 dq le 15 q5 d6 17 dq le 16 q6 d7 18 dq le 19 q7 figure 7. expanded logic diagram
74HC373 http://onsemi.com 8 package dimensions tssop ? 20 case 948e ? 02 issue c dim a min max min max inches 6.60 0.260 millimeters b 4.30 4.50 0.169 0.177 c 1.20 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.27 0.37 0.011 0.015 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ? w ? . 110 11 20 pin 1 ident a b ? t ? 0.100 (0.004) c d g h section n ? n k k1 jj1 n n m f ? w ? seating plane ? v ? ? u ? s u m 0.10 (0.004) v s t 20x ref k l l/2 2x s u 0.15 (0.006) t detail e 0.25 (0.010) detail e 6.40 0.252 ??? ??? s u 0.15 (0.006) t 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
74HC373 http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 74HC373/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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